Title :
IDDQ testing of opens in CMOS SRAMs
Author :
Champac, Victor H. ; Castillejos, José ; Figueras, Joan
Author_Institution :
Dept. of Electron. Eng., Nat. Inst. of Astrophys., Puebla, Mexico
Abstract :
The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the working phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (IDDQ) increases and the fault can be detected sensing the IDDQ. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by IDDQ testing. The cost of both proposed approaches is analyzed
Keywords :
CMOS memory circuits; SRAM chips; fault location; integrated circuit testing; CMOS SRAMs; IDDQ testing; cost analysis; data retention faults; destructive read-out; fault detection; open defects; power supply level control; precharge level; quiescent current consumption; sequential access; Circuit faults; Circuit testing; Costs; Electronic equipment testing; Fault detection; Logic testing; Power supplies; Random access memory; Voltage; Writing;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670856
