Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA

The Wave Dynamic Differential Logic (WDDL) offers an affective way to address Differential Power Attack (DPA). However, the effectiveness of this countermeasure is guaranteed provided the routing of both the real and complementary paths is balanced, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem of timing unbalance. First, we propose dual placement techniques, and quantify the gain that they confer. Then, we introduce a simple but effective new timing-balance driven router based on the PathFinder algorithm. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 92% in delay balance, while keeping reasonable overhead both in terms of the number of switches used for routing and the critical path delay.