Robustly testable array multipliers under realistic sequential cell fault model

Author

Psarakis, Mihalis ; Gizopoulos, Dimitris ; Paschalis, Antonis ; Zorian, Yeravnt

Author_Institution

Inst. of Inf. & Telecommun., Athens, Greece

fYear

1998

fDate

26-30 Apr 1998

Firstpage

152

Lastpage

157

Abstract

Traditional combinational fault models are not sufficient to detect to most common failure mechanisms in CMOS Iterative Logic Arrays (ILAs). The Realistic Sequential Cell Fault Model (RS-CFM) provides a comprehensive, robust test methodology for ILAs. It also satisfies the requirements for low test complexity and cell implementation independence. Adopting RS-CFM, we first provide sufficient conditions for two-dimensional (2D) ILAs to be robustly testable for first time in the literature. Then, we propose sufficient modifications to the carry-save and carry-propagate array multipliers so that they can be treated robustly with respect to RS-CPM with a test set of linear size

Keywords

CMOS logic circuits; VLSI; carry logic; design for testability; fault diagnosis; integrated circuit testing; logic arrays; logic design; logic testing; multiplying circuits; sequential circuits; CMOS iterative logic arrays; carry-propagate array multipliers; carry-save array multipliers; cell implementation independence; linear size test set; low test complexity; realistic sequential cell fault model; robust test methodology; robustly testable array multipliers; sequential faults; two-dimensional ILA; Circuit faults; Circuit testing; Fault detection; Gas detectors; Integrated circuit modeling; Integrated circuit testing; Logic arrays; Robustness; Sequential analysis; Tellurium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670863

Filename

670863