Title :
Estimation of error detection probability and latency of checking methods for a given circuit under check
Author :
Kuchukyan, Arsen
Author_Institution :
System Test & Reliability Lab., American Univ. of Armenia, Yerevan, Armenia
Abstract :
A technique of sampling of input vectors (SIV) with statistical measurements is used for the estimation of error detection probability and fault latency of different checking methods. Application of the technique for Berger code, mod3 and parity checking for combinational circuits is considered. The experimental results obtained by a Pilot Software System are presented. The technique may be implemented as an overhead to an already existing fault simulator
Keywords :
combinational circuits; computational complexity; logic testing; Berger code; Pilot Software System; circuit under check; combinational circuits; error detection; error detection probability; fault latency; latency; mod3; parity checking; probability; sampling of input vectors; Application software; Circuit faults; Combinational circuits; Delay; Electrical fault detection; Estimation error; Fault detection; Probability; Sampling methods; Software systems;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670891
