Title :
A low-leakage current power 180-nm CMOS SRAM
Author :
Enomoto, Tadayoshi ; Higuchi, Yuki
Author_Institution :
Chuo Univ., Tokyo
Abstract :
A low leakage power, 180-nm 1K-b SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a "self-controllable voltage level (SVL)" circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8 V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.
Keywords :
CMOS digital integrated circuits; SRAM chips; leakage current reduction circuit; low-leakage current power CMOS SRAM; memory cell array; power 3.8 nW; self-controllable voltage level circuit; size 180 nm; voltage 1.8 V; Decoding; Leakage current; MOSFET circuits; Power supplies; Random access memory; Resistors; Switches; Switching circuits; Variable structure systems; Voltage;
Conference_Titel :
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-1921-0
Electronic_ISBN :
978-1-4244-1922-7
DOI :
10.1109/ASPDAC.2008.4483914
