• DocumentCode
    3228870
  • Title

    CAM puzzle: A power model and function-based circuit segment method of Content Addressable Memory

  • Author

    Sio, Kam-Tou ; Lai, Feipei ; Peng, Chin-Hung

  • Author_Institution
    Grad. Inst. of Biomed. Electron. & Bioinf., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2010
  • fDate
    6-9 Dec. 2010
  • Firstpage
    304
  • Lastpage
    307
  • Abstract
    Content Addressable Memory (CAM) is a data storage device, utilizing the Static Random Access Memory (SRAM) cell. CAMs are very popular especially implemented in network routers for IP address lookup, packet forwarding and packet classifications. Up to now, there are many types of CAM to conform to these different implementations. For the purpose to estimate the efficiency and power distribution of all types of CAM, doing preliminary simulation is needed before doing concrete circuit layout. Therefore, a speedy and accurate power analysis method is necessary. Besides, the simulation time of nowadays circuit simulation tool like HSPICE is considerable, especially for high frequency data storage circuits like CAMs. This work established a brand new power model of CAM which is called CAM Puzzle (CAMP), combining the petty models which are extracted from SPICE simulation, simplified into easily analytical power expressions in order to analyse the conventional CAM and pre-computation based content addressable memory (PB-CAM). In addition, this work also estimates the power consumption of CAM peripheral circuits such as address decoder circuit and data I/O. Using CAMP, the power consumption of complete CAM architecture can be estimated with 82% model accuracy and 94% system accuracy compared to SPICE simulation in 0.18μm process.
  • Keywords
    IP networks; SPICE; SRAM chips; circuit simulation; content-addressable storage; integrated circuit layout; memory architecture; network routing; CAM architecture; CAM peripheral circuits; CAM puzzle; CAMP; HSPICE; IP address lookup; PB-CAM; SPICE simulation; SRAM cell; address decoder circuit; circuit simulation tool; concrete circuit layout; conventional CAM; data I/O; data storage device; function-based circuit segment method; high frequency data storage circuits; network routers; packet classifications; packet forwarding; petty models; power analysis method; power consumption; power distribution; power expressions; power model; precomputation based content addressable memory; preliminary simulation; simulation time; static random access memory cell; Accuracy; CMOS integrated circuits; Computer aided manufacturing; Decoding; Integrated circuit modeling; Logic gates; Semiconductor device modeling; CAM; PB-CAM; SPICE simulation; accuracy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4244-7454-7
  • Type

    conf

  • DOI
    10.1109/APCCAS.2010.5774881
  • Filename
    5774881