Title :
High-speed and low power unified dual-field multiplier in GF (P) and GF (2m)
Author :
Shrivastava, Prabhat Chandra ; Kumar, Rupesh ; Kumar, Arvind ; Rai, Sanjeev
Author_Institution :
Dept. of Electron. & Commun. Eng., Motilal Nehru Nat. Inst. of Technol., Allahabad, India
Abstract :
This paper presents a new hardware architecture for a unified multiplier, which operates in two types of finite field: GF (P) and GF (2m). We present a simple but highly useful modification of the conventional hardware implementation of accumulation in finite field over GF (P) and GF (2m). This new design uses parallel one´s counters to accumulate the binary partial product bit in GF (P) and further uses a T flip-flop for binary extension field. The proposed multiplier in GF (2m) achieves 11.76% and 30.23% gain in speed for (8, 16, 32) and (64, 128) bit operands respectively and an average 3.92% reduction in power consumption. The unified dual field multiplier achieves 19.3% and 14.3% gain in speed and reduction in power consumption respectively for 8 bits operand. The proposed multiplier is scalable for operands of any size. The multiplier uses the LSB-first bit serial architecture for multiplication in GF (P) and GF (2m), other than Montgomery multiplication algorithm, which mostly employs existing dual field multipliers.
Keywords :
Galois fields; low-power electronics; multiplying circuits; public key cryptography; LSB-first bit serial architecture; binary extension field; binary partial product bit; finite field; hardware architecture; low power unified dual-field multiplier; Computer architecture; Delay; Finite element methods; Galois fields; Hardware; Polynomials; Registers; Elliptical curve cryptography (ECC); Galois field (GF); VLSI; finite field addition; finite field multiplication; irreducible All one polynomial (AOP);
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5774883