Title :
Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits
Author :
Huang, Hung-Yen ; Huang, Yu-Sheng ; Hsu, Chun-Lung
Author_Institution :
Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan
Abstract :
This paper presents a built-in self-test/repair (BISTR) scheme for through-silicon via (TSV) based three-dimension integrated circuits (3D ICs). The proposed BIST structure focuses on the testing of a specific defective TSV by using a critical value of threshold. Then, the test results from BIST will be delivered to the BISR structure for repairing the defective TSV. Additionally, a parallel processing approach is presented of the proposed BISTR scheme to speed up the operations of test and repair. Experimental results demonstrate that the proposed BISTR scheme can achieve the good performance in repair rate and yield with little area overhead penalty.
Keywords :
built-in self test; integrated circuit testing; integrated circuit yield; parallel processing; three-dimensional integrated circuits; 3D IC; BISTR scheme; TSV-based three-dimensional integrated circuit; built-in self-test/repair; defective TSV; parallel processing; repair rate; through-silicon via; yield; Benchmark testing; Built-in self-test; Maintenance engineering; Parallel processing; Three dimensional displays; Through-silicon vias; 3D IC; BISR; BIST; TSV; area overhead; yield;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5774885
