DocumentCode
3228946
Title
DynaNP - A Coarse-grain Dataflow Network Processor Architecture with Dynamic Configurable Processing Path
Author
Li, Tao ; Zhang, Xiao-Ming ; Sun, Zhi-Gang
Author_Institution
Nat. Univ. of Defense Technol., Changsha
Volume
3
fYear
2007
fDate
July 30 2007-Aug. 1 2007
Firstpage
182
Lastpage
187
Abstract
Aimed at the limitation of ILP exploitation and the fixed topology of control-flow NP, a new scheme of coarse-grain dataflow NP architecture - DynaNP is proposed. DynaNP can not only improve the programmability of NP by adopting control-flow structure in each processing element (PE), but also effectively exploit the task-level parallelism by introducing data-flow model into the processing of multiple PEs. A mechanism of dynamic configurable processing path is also provided in DynaNP. Art S-DTPPS algorithm based on dynamic configurable processing path is proposed in DynaNP. The simulation results show that by using this algorithm the load of each PE can be balanced efficiently and the overall throughput of DynaNP will be improved.
Keywords
data flow computing; microprocessor chips; parallel algorithms; parallel architectures; Art S-DTPPS algorithm; DynaNP; coarse-grain dataflow network processor architecture; control-flow structure; dynamic configurable processing path; processing element; Artificial intelligence; Computer architecture; Distributed computing; Parallel processing; Pipelines; Signal processing; Software engineering; Sun; Throughput; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing, 2007. SNPD 2007. Eighth ACIS International Conference on
Conference_Location
Qingdao
Print_ISBN
978-0-7695-2909-7
Type
conf
DOI
10.1109/SNPD.2007.384
Filename
4287846
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