A new offset cancelled latch comparator for high-speed, low-power ADCs

A new high speed, low power and high resolution comparator architecture is presented. Offset voltage cancellation on latch stage and eliminating the preamplifier stages before regeneration latch in conventional architectures is the key idea proposed in this paper. Equivalent input referred offset voltage is dramatically reduced by controlled negative feedback loop and negative resistance of regeneration latch. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 0.2 mV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator operates in 500 MHz clock frequency while dissipates 600 μW from a 1.8V supply.