Title :
An all-digital de-skew clock generator for arbitrary wide range delay
Author :
Fong, Kevin ; Hung, Yu-Cheng ; Chen, Zuow-Zun ; Lee, Tai-Cheng
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS technology. The clock generator achieves a measured RMS jitter of 8.3 ps at an 800-MHz clock with 10 cycles settling time. The chip area is 0.825×0.605 mm2 and the power consumption is 53mW from a 1.8V supply.
Keywords :
CMOS integrated circuits; clocks; delay lock loops; CMOS technology; all-digital de-skew clock generator; arbitrary wide range delay; clock skew problem; frequency 800 MHz; power 53 mW; size 0.18 mum; time 8.3 ps; voltage 1.8 V; Clocks; Delay; Delay lines; Generators; Jitter; Switches; Synchronization; De-skew clock generator; delay-locked loop (DLL); synchronous mirror delay (SMD);
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5774895
