Low power, variable resolution pipelined analog to Digital converter with sub flash architecture

In this paper, a design for low power pipelined Analog to Digital converter with self configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused stages to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 8-bit, 10-bit and 12-bit precision at a supply voltage of 1.2V; it consumes 25mW at 12-bit, 20mW at 10-bit and 15mW at 8-bit resolution. The sampling frequency ranges upto 150 Msps, and the ADC has a DNL <; ±0.25LSB, INL <; ±0.5LSB, SNR of 71.5dB and SNDR of 69.1dB for 12-bit operation. The performance of the ADC is verified in post layout simulations at 65nm technology node.