Title :
Floating-point reconfiguration array processor for 3D graphics physics engine
Author_Institution :
Core Logic, Seoul
Abstract :
We implemented an RTL model of the proposed RA and perform simulation in RealView coverification environment by executing examples using physics engine. We discovered if the physics engine part is accelerated by RA, the workloads run over 20 times faster than the pure software without FPU and over 4 times faster than the pure software with FPU. If codes are well partitioned and optimized for the proposed RA, which now remains for future study, even more improvement can be expected.
Keywords :
computer graphics; system-on-chip; 3D graphics physics engine; RealView coverification environment; SOC; floating-point reconfiguration array processor; system-on-chip; Acceleration; Codecs; Energy consumption; Engines; Floating-point arithmetic; Graphics; Hardware; Multimedia systems; Physics; Rabbits;
Conference_Titel :
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-1921-0
Electronic_ISBN :
978-1-4244-1922-7
DOI :
10.1109/ASPDAC.2008.4483956
