FPGA implementation for image object detection system on NoCs

This paper presents a routing approach for the mesh network on chip. This routing approach can choose the appropriate intermediate router to achieve the fast routing. It can balance the traffic load and achieve deadlock free. From the experimental results, our approach can improve at least 8.3% of the packet transmission latency comparing with the latest works. Next, the image object detection system, which includes 5 hardware intellectual properties and mesh network, is implemented in a FPGA platform. The total logic element is about 27,912, and the memory bits are 680,216. Its working frequency is 25 MHz such that it can process 22 frames per second for 320*240 image size.