An FPGA implemented 24-bit audio DAC with 1-bit sigma-delta modulator

This paper presents the design and FPGA implementation of a 24-bit audio DAC incorporating a set of multiplier-free interpolation filters and a 4th-order 1-bit sigma-delta modulator (SDM). The whole system achieves a signal to noise ratio (SNR) as high as 139dB with idle tones and noise modulation virtually eliminated. For the fixed point interpolation filters, multiplier-free canonical signed digits (CSD) coefficients are chosen to sharply reduce FPGA resources utilization. And the zeros of SDM are psychoacoustically optimized to minimize the total perceived output noise power so that the resultant noise within the signal band becomes unobjectionable to the human ear. Furthermore, in order to eliminate the idle tones notorious in 1-bit SDM, single-bit dither of ±0.125 amplitude is added while guaranteeing a maximum stable input range of -5.19dBFS.