DocumentCode :
3230244
Title :
Low power CMOS-magnetic nano-logic with increased bit controllability
Author :
Das, Jayita ; Alam, Syed M. ; Bhanja, Sanjukta
Author_Institution :
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
fYear :
2011
fDate :
15-18 Aug. 2011
Firstpage :
1261
Lastpage :
1266
Abstract :
Conventional magnetic logic using single-domain nanomagnets face severe challenges from power consumption, during field induced writing and clocking, and from poor selectivity over the logic cells. In this paper we report a novel CMOS integrated nanomagnetic logic architecture using Magnetic Tunnel Junctions (MTJs) as elemental cells. The integration details with 22nm CMOS technology is discussed and the feasibility of integration studied. The access transistors of the MTJs provide certain improvement in controllability over the bits of the logic. Increased controllability prevents unnecessary switching of the cells, as discussed in the paper, and hence saves power.
Keywords :
CMOS logic circuits; low-power electronics; magnetic tunnelling; nanomagnetics; CMOS integrated nanomagnetic logic architecture; access transistors; bit controllability; logic cells; low power CMOS; magnetic tunnel junctions; power consumption; size 22 nm; Clocks; Computer architecture; Magnetic tunneling; Magnetization; Switches; Transistors; Wires; Hybrid CMOS-nanomagnetic architecture; low power; nanomagnetic logic; spintronic logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
ISSN :
1944-9399
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
Type :
conf
DOI :
10.1109/NANO.2011.6144605
Filename :
6144605
Link To Document :
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