Low power level shifter and combined with logic gates

As the portable electronic products have being used extensively, many complex logic and mathematic functions need to be operated at low supply voltage for low power requirement. Different function blocks may need different supply voltages based on the performance requirements. With the emphasis on the efficiency in the transistor level, a novel level shifter is proposed. The proposed designs embedded within the conventional digital logic gates are investigated. Compared to other counterparts, the proposed design can achieve an average of 7 times smaller in the power delay product. The design is implemented in TSMC 90nm 1P9M process.