A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators

A clock generation technique for reducing the clock-jitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digital elements to generate a fixed-pulse-width feedback control clock. It was verified in a 2^nd order, 1-bit CT ΣΔ modulator with SI RZ feedback. Simulation result shows that the clock-jitter tolerance using the proposed technique is up to 2% of a clock cycle with SNDR larger than 62dB. While using the traditional clock generation method, clock-jitter tolerance is only 0.1% of a clock cycle.