DocumentCode :
3230380
Title :
Dynamic wordlength calibration to reduce power dissipation in wireless OFDM systems
Author :
Kim, Jaeseong ; Yoshizawa, Shingo ; Miyanaga, Yoshikazu
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
fYear :
2010
fDate :
6-9 Dec. 2010
Firstpage :
628
Lastpage :
631
Abstract :
This paper describes low power architecture by using a dynamic wordlength technique in wireless orthogonal frequency division multiplexing (OFDM) system. The number of wordlength in digital signal processing (DSP) has to be carefully determined because wordlength affects system performance and hardware cost. Dynamic wordlength technique is applied to a fast Fourier transform (FFT) processor and a Viterbi decoder in OFDM receiver. The proposed method searches an optimum wordlength combination of FFT processor and Viterbi decoder by comparing output binary data while changing wordlengths. This operation is done by use of intervals in packet waiting. This approach leads to achieve the power reduction up to 23.9% with a desirable packet error rate (PER) in multipath channel environment.
Keywords :
OFDM modulation; Viterbi decoding; digital signal processing chips; error statistics; fast Fourier transforms; multipath channels; DSP; FFT processor; OFDM receiver; PER; Viterbi decoder; digital signal processing; dynamic wordlength calibration; fast Fourier transform; low power architecture; multipath channel environment; packet error rate; power dissipation; wireless OFDM system; wireless orthogonal frequency division multiplexing; Clocks; Decoding; Demodulation; OFDM; Receivers; Viterbi algorithm; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
Type :
conf
DOI :
10.1109/APCCAS.2010.5774944
Filename :
5774944
Link To Document :
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