DocumentCode :
3230391
Title :
A concurrent low-area dual band 0.9/2.4 GHz LNA in 0.13µm RF CMOS technology for multi-band wireless receiver
Author :
Datta, Sambit ; Datta, Kunal ; Dutta, Ashudeb ; Bhattacharyya, Tarun Kanti
Author_Institution :
Electron. & Electr. Commun. Eng. Dept., IIT Kharagpur, Kharagpur, India
fYear :
2010
fDate :
6-9 Dec. 2010
Firstpage :
280
Lastpage :
283
Abstract :
This article presents the design of a low area novel concurrent dual-band LNA operating in the GSM 0.9GHz/BLUETOOTH 2.4GHz communication standards. The concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. A conventional source degeneration inductor is eliminated for higher signal gain while providing reasonable input impedance. Also by adding a capacitor between the gate and the source of the input transistor, a noise source from the gate resistance is partly suppressed. The output matching network is constructed of shunt peaking. It´s easy to achieve matching and reduced chip size. The current design is especially suitable for use in multi-standard wireless receiver frontends as it saves die area and reduces power consumption by replacing parallel LNAs for each channel frequency. Simulation results indicate a Noise Figure below 2dB and S21 above 14 dB in all frequency bands and also input and output return loss are below -10 dB for all desired frequency band while drawing 10mA current from a 1.2V power supply.
Keywords :
Bluetooth; CMOS integrated circuits; capacitors; cellular radio; electric resistance; low noise amplifiers; radio receivers; radiofrequency integrated circuits; wireless channels; Bluetooth; CADENCE; GSM; RF CMOS technology; UMC technology; capacitor; channel frequency; communication standard; concurrent low-area dual band LNA; current 10 mA; frequency 0.9 GHz; frequency 2.4 GHz; gate resistance; input impedance; multiband wireless receiver; multistandard wireless receiver; noise source; output matching network; power consumption; signal gain; size 0.13 mum; transistor; voltage 1.2 V; CMOS integrated circuits; Dual band; Impedance matching; Inductors; Logic gates; Noise; Transistors; BLUETOOTH; Dual-band concurrent Low Noise Amplifier; GSM; concurrent Input Matching Network;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
Type :
conf
DOI :
10.1109/APCCAS.2010.5774945
Filename :
5774945
Link To Document :
بازگشت