DocumentCode
3230406
Title
Latency and power consumption in unstructured nanoscale boolean networks
Author
Amarnath, Avinash ; Damera, Prateen ; Goudarzi, Alireza ; Teuscher, Christof
Author_Institution
Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA
fYear
2011
fDate
15-18 Aug. 2011
Firstpage
854
Lastpage
859
Abstract
The self-assembly of nanoelectronic devices may result in network of heterogeneous components with an unstructured interconnect. It has been shown that the fan-in of two per gate optimizes the number of required gates in logical blocks for feed-forward networks of gates. On the other hand, the local connectivity in a mesh network optimizes the interconnects energy consumption. In this paper, we address the question of what fan-in optimizes both the power consumption and the latency in an unstructured network. We show that an average fan-in of K = 3.3 is optimal for random Boolean networks when energy and latency are considered equally important. Our results are important as they show an inverse relationship between the energy consumption and the performance, and this allow us to determine the optimal connectivity of a certain class of self-assembled nanoscale devices.
Keywords
Boolean functions; CMOS logic circuits; logic gates; nanoelectronics; power consumption; self-assembly; energy consumption interconnect; feedforward gate network; heterogeneous component; latency consumption; logical block; mesh network; nanoelectronic devices self-assembly; optimal connectivity; power consumption; random Boolean network; self-assembled nanoscale device; two per gate fan-in; unstructured nanoscale Boolean network; Artificial intelligence; Capacitance; Computer languages; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location
Portland, OR
ISSN
1944-9399
Print_ISBN
978-1-4577-1514-3
Electronic_ISBN
1944-9399
Type
conf
DOI
10.1109/NANO.2011.6144611
Filename
6144611
Link To Document