Optimizing APT product in MBFA topologies

In this paper, we propose addressing schemes to optimize Area Power Timing (APT) product, utilizing data dependency in Majority Based Full Adder (MBFA) topologies. With advancement in technology and demand of portability in applications, all the design parameters of a digital design viz. Area Power and Timing requirement have become equally important. As all the three need to be as small as possible, we have focused our work to optimize the APT product. MBFA topologies promise better area requirements as the number of transistors are reduced compared to conventional adder topologies. As we have realized these adders using single Vt transistors, the power consumption increases compared to other topologies but based on the nature of incoming data a significant improvement in power requirement is obtained. The addressing schemes proposed in this paper help in reducing power consumption of MBFA by a factor of two, when used in address calculation. The adders are studied in 180nm CMOS process technology using a supply voltage of 1.8V.