DocumentCode :
3230471
Title :
Design and analysis of a novel reversible encoder/decoder
Author :
Nachtigal, Michael ; Ranganathan, Nagarajan
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear :
2011
fDate :
15-18 Aug. 2011
Firstpage :
1543
Lastpage :
1546
Abstract :
Reversible computation differs from traditional computation in that it preserves information while manipulating it. This new design paradigm has very attractive thermodynamic consequences and holds many applications in current and emerging technologies. Modern computers can reduce power consumption by taking advantage of reversibility, and quantum computers operate reversibly. Researchers have already proposed reversible designs of many common arithmetic and logical units, including adders, multipliers, shifters, and even registers. Very little focused work has been done specifically on reversible encoder/decoder design. In this paper we propose a novel reversible encoder/decoder design and analyze it in terms of its quantum cost, garbage outputs, constant inputs, and quantum delay.
Keywords :
adders; decoding; delays; digital arithmetic; encoding; logic circuits; multiplying circuits; quantum computing; shift registers; thermodynamics; adder; arithmetic unit; constant input; even register; garbage output; logical unit; multiplier; power consumption; quantum computer; quantum cost; quantum delay; reversible encoder-decoder design; shifter; thermodynamic consequence; Computer science; Computers; Decoding; Delay; Logic gates; Quantum computing; Reversible logic; binary; decoder; encoder; quantum computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
ISSN :
1944-9399
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
Type :
conf
DOI :
10.1109/NANO.2011.6144615
Filename :
6144615
Link To Document :
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