DocumentCode :
3230475
Title :
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Author :
Das, Debasish ; Killpack, Kip ; Kashyap, Chandramouli ; Jas, Abhijit ; Zhou, Hai
Author_Institution :
Northwestern Univ., Evanston
fYear :
2008
fDate :
21-24 March 2008
Firstpage :
486
Lastpage :
491
Abstract :
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been proposed, the results are often pessimistic with many false failures. We present an integrated iterative timing filtering and logic filtering based approach to reduce pessimism. We use a realistic coupling model based on arrival times and slews and show that non-iterative pessimism reduction algorithms proposed in previous research may give potentially non- conservative timing results. On a functional block from an industrial 65nm microprocessor, our algorithm produced a maximum pessimism reduction of 11.18% of cycle time over converged timing filtering analysis that does not consider logic constraints.
Keywords :
delays; integrated circuit modelling; iterative methods; microprocessor chips; nanoelectronics; coupling-aware static timing analysis; delay variations; integrated iterative timing filtering; logic filtering; pessimism reduction; size 65 nm; Algorithm design and analysis; Capacitance; Delay; Filtering algorithms; Iterative algorithms; Iterative methods; Logic; Switches; Timing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-1921-0
Electronic_ISBN :
978-1-4244-1922-7
Type :
conf
DOI :
10.1109/ASPDAC.2008.4483999
Filename :
4483999
Link To Document :
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