Title :
A multiphase all-digital delay-locked loop with reuse SAR
Author :
Chen, Pao-Lung ; Wang, Tzu-Siang ; Ciou, Jyun-Han
Author_Institution :
Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Kaohsiung, Taiwan
Abstract :
A multiphase all-digital delay-locked loop (DLL) with reuse SAR has been designed with TSMC 0.18μm CMOS technology. The proposed reuse successive approximation register (Reuse SAR) reduces the hardware cost effectively as compared with a conventional SAR or a two-stage SAR. The digital to voltage convertor has six coarse controlled bits and six fine controlled bits to adjust voltage for voltage controlled delay line. The core area is 206.8 μm × 217.4 μm and power consumption is 22.6 mW at 125 MHz.
Keywords :
CMOS digital integrated circuits; delay lines; delay lock loops; digital-analogue conversion; TSMC CMOS technology; digital to voltage convertor; frequency 125 MHz; multiphase all-digital delay-locked loop; power 22.6 mW; power consumption; reuse SAR; reuse successive approximation register; size 0.18 mum; voltage controlled delay line; Clocks; Delay; Delay lines; Generators; MOS devices; Solid state circuits; Voltage control; Delay-locked loop (DLL); Digital to voltage convertor (DVC); Multiphase; Reuse successive; approximation register (Reuse SAR);
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5774957
