Hardware implementation of a high speed floating point multiplier based on FPGA

The hardware implementation of a high speed floating point multiplier with pipeline architecture based on FPGA is presented in the paper. In the design of the floating point multiplier, the utilization of a new radix-4 booth´s encoding algorithm, the improved 4:2 compression structure and summation circuit is made to implement the compression of the partial products, and the sum and carry vectors are added by a final carry look-ahead adder to obtain the product. The timing simulation results show that the floating point multiplier can be steadily run at the frequency of 80 MHz. The multiplier has been adopted in the FFT processor successfully.