An improved design method for multi-bits reused booth multiplier

Author

Yi, Qian ; Han Jing

Author_Institution

Dept. of Inf. Sci. & Technol., Taishan Univ., Taian, China

fYear

2009

fDate

25-28 July 2009

Firstpage

1914

Lastpage

1916

Abstract

In order to solve the question for the 32-bit multiplier to do a variety of bit-length multiplication fast in the form of reusing resource on the FPGA, radix-4 booth modified algorithm is studied, and a bit-length controller is designed to control some bits, partial product generator and fast adder´s structure are improved, so as to reuse most of the hardware resource in 8-bit or 16-bit multiplication. The multiplier works with not only 32-bit but also two 16-bit or four 8-bit data at one clock, ensures the speed and saves the chip area at the same time.

Keywords

adders; field programmable gate arrays; logic design; multiplying circuits; 32-bit multiplier; FPGA; bit-length controller; bit-length multiplication; fast adder structure; field programmable gate arrays; multibit reused booth multiplier; radix-4 booth modified algorithm; Algorithm design and analysis; Clocks; Computer science; Computer science education; Design methodology; Field programmable gate arrays; Hardware; Information science; Parallel processing; Signal processing algorithms; booth; multi-bits; multiplier; reuse;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science & Education, 2009. ICCSE '09. 4th International Conference on

Conference_Location

Nanning

Print_ISBN

978-1-4244-3520-3

Electronic_ISBN

978-1-4244-3521-0

Type

conf

DOI

10.1109/ICCSE.2009.5228243

Filename

5228243