DocumentCode
3230781
Title
A hybrid architecture for efficient FPGA-based implementation of multilayer neural network
Author
Lin, Zhen ; Dong, Yiping ; Li, Yan ; Watanabe, Takahiro
Author_Institution
Grad. Sch. of Inf., Waseda Univ., Kitakyushu, Japan
fYear
2010
fDate
6-9 Dec. 2010
Firstpage
616
Lastpage
619
Abstract
This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.
Keywords
field programmable gate arrays; multilayer perceptrons; network topology; neural chips; pipeline processing; FPGA; NN schematic; compact circuit; forward speed; hybrid architecture; layer-multiplexing; mapping method; multilayer neural network; neural network topology; physical architecture; pipeline architecture; resource usage; Artificial neural networks; Field programmable gate arrays; Network topology; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
978-1-4244-7454-7
Type
conf
DOI
10.1109/APCCAS.2010.5774961
Filename
5774961
Link To Document