DocumentCode
3230914
Title
An energy-efficient successive approximation register analog to digital converter in 180nm
Author
Kuntz, Taimur Gibran Rabuske ; Nooshabadi, Saeid
Author_Institution
Microelectron. Group, Fed. Univ. of Santa Maria (UFSM), Santa Maria, Brazil
fYear
2010
fDate
6-9 Dec. 2010
Firstpage
764
Lastpage
767
Abstract
This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations. This FOM is close to reference designs reported in 90nm.
Keywords
analogue-digital conversion; asynchronous circuits; analog-to-digital converter; asynchronous logic circuitry; charge sharing; energy-efficient successive approximation register; figure of merit; reference designs; sampling scheme; scaled digital voltage supply; size 180 nm; size 90 nm; state-of-the-art techniques; Approximation methods; Arrays; CMOS integrated circuits; Capacitors; Power demand; Topology; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
978-1-4244-7454-7
Type
conf
DOI
10.1109/APCCAS.2010.5774967
Filename
5774967
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