• DocumentCode
    3230995
  • Title

    A hardware-efficient color segmentation algorithm for face detection

  • Author

    Hu, Kai-Ti ; Pai, Yu-Ting ; Ruan, Shanq-Jang ; Naroska, Edwin

  • Author_Institution
    Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
  • fYear
    2010
  • fDate
    6-9 Dec. 2010
  • Firstpage
    688
  • Lastpage
    691
  • Abstract
    This paper develops a hardware-efficient color segmentation algorithm that is especially suitable to implement on hardware for face detection. Since the modulized design is adopted in the proposed algorithm without floating-point operation, the computational cost is directly reduced for hardware design. The proposed algorithm consists of a color space modeling module and a feature enhancement module. The significant skin/lip color features distribution can be accurately detected by using our proposed algorithm to facilitate the face detection. The proposed algorithm was implemented on a field-programmable gate array (FPGA) system for verifying its efficiency. Compared with other state-of-the-art algorithms, the proposed algorithm can significantly decrease the computational cost of the hardware implementation by using color segmentation instead of the overall analysis of the color distribution. Experimental results have verified that our proposed FPGA system occupies only 3,202 logic cells, or about five times less than the current comparable FPGA system with better detection rate.
  • Keywords
    face recognition; field programmable gate arrays; image colour analysis; image enhancement; image segmentation; object detection; FPGA system; color space modeling module; face detection; feature enhancement module; field-programmable gate array system; floating-point operation; hardware-efficient color segmentation algorithm; modulized design; skin-lip color features; Algorithm design and analysis; Face; Face detection; Feature extraction; Hardware; Image color analysis; Skin; Color segmentation; face detection; field-programmable gate array (FPGA);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4244-7454-7
  • Type

    conf

  • DOI
    10.1109/APCCAS.2010.5774971
  • Filename
    5774971