Modeling and optimization of wafer radial yield

The semiconductor industry has known for a long time that wafer functional test yields tend to degrade with closer proximity of the wafer perimeter. As the general long-term industry trend continues toward larger wafer diameters, the productivity impact of a radial yield component becomes increasingly more significant. For example, the migration from 200 mm to 300 mm wafers will create approximately 60% more chips bordering the wafer perimeter, for an average 12 mm×12 mm chip size. Radial yield is a measurable function and is often characterized by many semiconductor manufacturers; however, most manufacturers neglect to carefully manage this component like other key productivity parameters. This paper describes some methods used at IBM Microelectronics´ Vermont facility to characterize and optimize the radial yield loss component of the wafer final test yield. The strategies include tooling modifications and recipe changes, as well as wafer layout modifications. It has also been observed that product design content modulates the magnitude of the radial yield component. Two modeling techniques used to account for radial yield loss are discussed: one assumes the radial yield to contribute as a systematic limited yield; the other incorporates it into the random defect density model. This paper also contrasts the radial yield impacts and the productivity boundaries defined by the wafer exclusion ring