• DocumentCode
    3231209
  • Title

    Haystack syndrome avoidance on massive correlation for probe vs. E-test data through the concurrent use of tree base models and trellis graphics. Application on sub-micron mix-signal product for the determination of the best process conditions for yield m

  • Author

    Ortega, Carlos ; Alonso, J. Ignacio ; Sobrino, Eliseo ; Bonal, Javier

  • Author_Institution
    Microelectron. Group, Lucent Technol., Madrid, Spain
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    76
  • Lastpage
    79
  • Abstract
    In an environment which requires an intensive capitalisation like the semiconductor industry, time-detection/time-reaction to any kind of yield degradation is a key issue. Abundant literature covers the existent methodologies and strategies to prevent, detect and react to the cosmetic defects. Even hardware solutions are available in the market which offer the possibility through product or control inspections to monitor them for the analysis of electrical measurements, performed at the end of the process sequence, and their relationships with yield predictors. The analysis of hundred of variables associated with a yield descriptor presents an important challenge from the statistical standpoint. We have developed a solution that allows an easier differentiation of the main contributor variables to the yield descriptor explanation as well as a graphical output of the analysis. The graphical output also includes the concept of multivariate analysis. Multivariate analysis accounts for the relationships of several different variables against each other. Trellis library provides excellent graphical solutions to this type of analysis
  • Keywords
    failure analysis; graphs; integrated circuit yield; statistical analysis; trees (mathematics); bin failures; electrical test parameters; graphical output; haystack syndrome avoidance; massive correlation; multivariate analysis; probe versus E-test data; process conditions; sub-micron mix-signal product; tree-based models; trellis graphics; trellis library; wafer yield degradation; yield descriptor; yield losses; yield maximisation; Degradation; Electric variables control; Electric variables measurement; Electronics industry; Hardware; Inspection; Monitoring; Performance analysis; Performance evaluation; Probes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI
  • Conference_Location
    Boston, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-5217-3
  • Type

    conf

  • DOI
    10.1109/ASMC.1999.798185
  • Filename
    798185