Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs

This paper describes a set of state-of-the-art race logic synthesis technologies for multithreaded/multi-core HDL (hardware description language) and ESL (electronic system level) simulators, such as V2Sim™ [1]. The new technologies aid V2Sim™ to automatically eliminate race logic in large-scale System-on-Chip (SoC) circuits [2.3], so that V2Sim™ multithreaded simulation results will be the same as that of 1-CPU simulation. Furthermore, the technologies do not require SoC designers to audit and fix their SoC circuits manually to eliminate race logic in their designs; and the technologies can further speedup V2sim™ simulation performance by reducing the SoC logic that V2sim™ needs to process in simulation. With the new technologies, V2sim™ can be readily used by SoC designers to significantly reduce their SoC development time and costs, and time to market.