Title :
Power consumption & reliability in NanoCMOS
Author_Institution :
PGMicro/PPGC-Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
Abstract :
Thermal issues is an important challenge in NanoCMOS chips. High temperatures can reduce the reliability, so it is important to reduce power consumption to improve reliability. It is necessary a change in physical design paradigms to reduce the needed amount of transistors to perform one task. This work shows a new approach to reduce the amount of transistors by using complex gates and a new set of EDA tools to generate any transistor network. Some results show an important reduction on power consumption, improving also circuit reliability.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; integrated circuit reliability; power consumption; semiconductor device reliability; EDA tool; complex gate; nanoCMOS chip; nanoCMOS reliability; physical design paradigm; power consumption; thermal issue; transistor network; CMOS integrated circuits; Integrated circuit reliability; Layout; Logic gates; Power demand; Transistors; EDA; NanoCMOS; Physical Design; Power Consumption; Reliability;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
DOI :
10.1109/NANO.2011.6144656
