Over complementary MOS logic for don´t care conditions

The propagation delay in CMOS gates strongly depends on the number of series PMOS and NMOS transistors in the pull-up and pull-down networks, respectively. Don´t care conditions are widely used for logic simplification. The PMOS block is built by the on-set (logic-1) and partial don´t-care terms; and then the NMOS block is constructed by the off-set (logic-0) and the remnant don´t-care terms. We don´t care what the output is to be the unused combination of the input variables because they are guaranteed never to happen. By the don´t-care conditions, this paper proposes an over-complementary MOS logic for circuit simplification. The key point of the over-complementary is that some don´t-care terms are selected by the PMOS and NMOS block simultaneously. Thus the circuit implementation can be further simplified. The proposed over-complementary MOS logic reduces the number of stacked PMOS and NMOS transistor, layout area cost, and junction capacitance. It also decreases power dissipation in normal condition. And the circuit is still working properly.