Critical dimension sample planning for sub-0.25 micron processes

Critical dimension (CD) control in lithography and etch processing is imperative in order to achieve optimum device yield and speed performance for semiconductor manufacturing. As linewidths are reduced, the sources of CD errors do not automatically scale, and the detection of process excursions becomes more critical. An optimized CD measurement sampling plan can ensure an economical baseline control and the effective detection of process excursions. In this paper, we discuss the strengths and weaknesses of existing measurement sampling, analysis, and control techniques in their ability to identify certain CD process exclusions. We present a comprehensive methodology to characterize the process baseline variations and process excursions. Sampling plan choices ape evaluated and based on the balance between leaving material at risk (beta error) and generating false alarms (alpha risk). With the availability of specific fab data such as wafer starts and die selling price, the sample planning model can be used to evaluate costs and risk of alternate sampling plans. Specific fab cost data also allows for the calculation of the cost optimal sampling plan for a given inspection capacity