An integrated trigger system for the PIERRE AUGER fluorescence detector

The PIERRE AUGER fluorescence detector is designed to monitor extensive air showers of energies greater than 10¹⁹ eV. We present a hierarchical trigger-system with hardware and software components for efficient data reduction and event recognition. The first-level trigger uses configurable hardware to allow a flexible and very effective background suppression, in minimum a factor 2·10 ³ larger than conventional approaches as used in the HiRes experiment. It is designed with the hardware description language VHDL and synthesized in one FPGA with about 75000 gates. Due to the excellent noise suppression in the first-level trigger, a software based solution on a digital signal processor is sufficient for the second- and third-level trigger