A high performance vertical Si nanowire CMOS for ultra high density circuits

In this work we investigate novel vertical Silicon nanowire (NW) based CMOS technology for logic applications. The performance and behaviour of two nanowire and single nanowire vertical CMOS inverter are simulated and analysed. It is seen that vertical NW MOSFET has a significant performance gain over corresponding FinFET technology. We show that nanowire based vertical CMOS offer up to 80% reduction in layout area, and nearly one order of magnitude reduction in power at the cost of 15% (two wire) and 40% (single diameter single wire) increased delay. The results show that vertical nanowire based CMOS technology has very high potential for ultra-low power applications and offers excellent overall performance for deca-nanoscale CMOS.