Impact of skew and jitter on the performance of VLSI interconnects

The timing characteristics and performance of high-speed VLSI circuits is greatly dependent on the interconnects which distribute power, clock and signal to the entire chip. The delay, power dissipation and cross-talk are the major design constraints for high performance VLSI interconnects. These non-ideal effects are dependent on temperature and timing constraint viz. skew and jitter. This paper presents in depth analysis of skew and jitter variation on the performance of VLSI interconnects. It is shown that variations of skew, jitter and temperature change the behaviour of coupled interconnect lines under different switching patterns. Results are obtained using SPICE simulations for 130nm technology node.