DocumentCode
3231812
Title
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process
Author
Mineyama, Akiko ; Ito, Hiroyuki ; Ishii, Takahiro ; Okada, Kenichi ; Masu, Kazuya
Author_Institution
Tokyo Inst. of Technol., Tokyo
fYear
2008
fDate
21-24 March 2008
Firstpage
97
Lastpage
98
Abstract
This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on global interconnects. The proposed on-chip TL interconnect can achieve 10.5 Gbps signaling and has smaller delay, smaller delay variation and better power efficiency than conventional on-chip interconnects at high-frequencies.
Keywords
CMOS integrated circuits; equalisers; integrated circuit metallisation; transmission lines; CMOS process; LVDS-type; global interconnects; low voltage differential signaling; on-chip interconnects; on-chip transmission line interconnect; passive equalizers; size 90 nm; CMOS process; Delay; Energy consumption; Equalizers; Frequency dependence; Inductors; Integrated circuit interconnections; Low voltage; Power transmission lines; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Conference_Location
Seoul
Print_ISBN
978-1-4244-1921-0
Electronic_ISBN
978-1-4244-1922-7
Type
conf
DOI
10.1109/ASPDAC.2008.4484069
Filename
4484069
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