Predicting failing bitmap signatures for memory arrays with critical area analysis

Author

Segal, Julie D. ; Ho, Tom ; Hodgkins, Bob ; Misic, Petar ; Lin, James ; Yegnashankaran, Mohan

Author_Institution

HPL Inc., San Jose, CA, USA

fYear

1999

fDate

1999

Firstpage

178

Lastpage

182

Abstract

Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can predict failing bitmap signatures and their frequencies for any memory circuit. The technique is demonstrated using a 0.25 μm SRAM technology. Results can be used for test optimization, redundancy planning, yield prediction, and determining process steps responsible for yield loss

Keywords

SRAM chips; cellular arrays; failure analysis; integrated circuit layout; integrated circuit reliability; integrated circuit yield; integrated memory circuits; probability; redundancy; 0.25 micron; SRAM technology; cell layout; critical area analysis; electrical faults; failing bitmap signatures prediction; inline defect data; memory arrays; redundancy planning; rule-based algorithm; test optimization; yield loss; yield prediction; Algorithm design and analysis; Circuit faults; Circuit simulation; Data mining; Failure analysis; Frequency; Predictive models; Probability; Redundancy; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5217-3

Type

conf

DOI

10.1109/ASMC.1999.798216

Filename

798216