Title :
A slew-rate controlled output driver with one-cycle tuning time
Author :
Kwak, Young-Ho ; Jung, Inhwa ; Kim, Chulwoo
Author_Institution :
Korea Univ., Seoul
Abstract :
A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1 V/ns to 3.6 V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18 um CMOS process, and the control block consumes 13.7 mW at 1 Gbps.
Keywords :
CMOS digital integrated circuits; driver circuits; integrated circuit design; CMOS process; bit rate 1 Gbit/s; low-power slew-rate controlled output driver; one-cycle lock time; one-cycle tuning time; open loop digital scheme; power 13.7 mW; size 0.18 mum; Clocks; Crosstalk; Delay; Detectors; Driver circuits; Inverters; Open loop systems; Phase locked loops; Signal generators; Voltage;
Conference_Titel :
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-1921-0
Electronic_ISBN :
978-1-4244-1922-7
DOI :
10.1109/ASPDAC.2008.4484070
