Title :
A 3-GHz, 22-ps/dec dynamic comparator using negative resistance combined with input pair
Author :
Chen, Bo-Wei ; Wang, Jen-Peng ; Tsai, Chia-Ming
Author_Institution :
Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
A high speed, low delay/log(ΔVin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(ΔVin) of the comparator is 22ps/dec and consumes 213μW at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.
Keywords :
CMOS integrated circuits; comparators (circuits); negative resistance circuits; CMOS process technology; dynamic comparator; frequency 3 GHz; input differential pair; negative resistance; power 213 muW; size 90 nm; voltage 1.2 V; voltage 25 mV; CMOS process; Delay; Latches; Power demand; Resistance; Transconductance; Transistors; Comparator; negative resistance; transconductance boosting;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5775017
