Delay-resistor implementation of integrators in biomimic artificial neurons

Author

Wells, Richard B. ; Barnes, Bruce

Author_Institution

MRC Inst., Idaho Univ., Moscow, ID, USA

Volume

4

fYear

2002

fDate

5-8 Nov. 2002

Firstpage

3186

Abstract

This paper presents an approach to leaky integrator implementation in biomimic artificial neurons. In this implementation, the delay inherent in MOSFET devices due to their parasitic capacitance is used in place of explicit capacitors to obtain a leaky integrator function. The resulting circuit realizes a nonlinear integrator with differing integration risetimes and falltimes. The MOSFET resistors are operated in the triode region. We discuss how such issues as gate bias levels and input/output signal swings affect the dynamic response of the integrator.

Keywords

MOSFET; analogue processing circuits; capacitance; integrating circuits; neural chips; resistors; MOSFET devices; MOSFET resistors; biomimic artificial neurons; delay-resistor implementation; dynamic response; gate bias levels; input/output signal swings; integration falltimes; integration risetimes; integrators; leaky integrator function; leaky integrator implementation; nonlinear integrator; parasitic capacitance; triode region; Capacitors; Delay; FETs; Linear circuits; MOSFET circuits; Neurons; Poles and zeros; RLC circuits; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

IECON 02 [Industrial Electronics Society, IEEE 2002 28th Annual Conference of the]

Print_ISBN

0-7803-7474-6

Type

conf

DOI

10.1109/IECON.2002.1182907

Filename

1182907