Title :
A 0.5V 6-bit scalable phase interpolator
Author :
Kumaki, Satoshi ; Johari, Abul Hasan ; Matsubara, Takeshi ; Hayashi, Isamu ; Ishikuro, Hiroki
Author_Institution :
Dept. of Electr. & Electr. Eng., Keio Univ., Yokohama, Japan
Abstract :
This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pseudo-pipelined architecture is proposed to realize resolution scalability and to reduce the circuit size and power consumption. By using a simple architecture, the proposed circuit operates at 0.5V at which conventional analog PI cannot operate. Slew rate of inverter chain is controlled by current starving technique to support phase interpolation at wide input frequency range. The PI was designed in 65nm-CMOS technology. The circuit simulation confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of 1.25 LSB. The power consumption is 0.12 μW/MHz.
Keywords :
CMOS analogue integrated circuits; invertors; CMOS technology; circuit simulation; circuit size; current starving technique; dual-input inverter; inverter chain; phase interpolation; power consumption; pseudo-pipelined architecture; resolution scalability; scalable phase interpolator; size 65 nm; slew rate; voltage 0.5 V; word length 6 bit; Delay; Moon; Oscillators; DLL; PLL; multi-phase oscillator; phase interpolator;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5775034
