Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors

This paper describes the Panning Sorter (PanS), a new architecture for hardware implementation of compact, fast, low power data sorters operating with parallel inputs. The proposed approach is compared against several other contemporary implementations (Systolic, Bitonic, Weave, and Insertion sorters) in order to demonstrate its features. The PanS architecture is then extended to the implementation of the Minimal-Hardware Panning Sorter (MH-PanS), capable of sorting data blocks of any size with just one compare-and-swap unit, which is the absolute minimum hardware complexity for this kind of processor. Experimental results, from implementations in an FPGA device for several data block sizes, are reported.