An output-capacitor-free cascode low-dropout regulator with low quiescent current and high power supply rejection

This paper presents the design of an output-capacitor-free cascode low-dropout regulator (LDR) with low quiescent current and high power supply rejection (PSR) over a wide range of frequency. In the proposed LDR topology, power NMOS transistors are cascoded to isolate the core regulator from power supply ripples, thus providing high PSR even without any external filtering capacitors. By biasing the cascoding NMOS transistors with ultra-low power auxiliary LDRs whose controllers draw currents from a voltage doubler, the whole system achieves high PSR with very low quiescent current consumption. System modeling and design issues are discussed. An experimental prototype was successfully fabricated with a standard 0.35-μm CMOS process, occupying an active chip area of 0.092 mm². The input is 1.8 V and the preset output is 1.2 V with a maximum load current of 10 mA. The quiescent current at no load is only 39 μA. The measured PSR at full load is better than -37.5 dB up to 50 MHz, without using off-chip capacitors. The line and load regulations are 0.45 mV/V and 0.50 mV/mA, respectively.