Interconnect constraints on BEOL manufacturing

Author

Mangaser, Ramon ; Mark, Christopher ; Rose, Kenneth

Author_Institution

Center for Adv. Interconnect Sci. & Technol., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

1999

fDate

1999

Firstpage

304

Lastpage

308

Abstract

As CMOS devices are scaled to deep submicron dimensions, BEOL manufacturability will be constrained by both global and short local interconnects. The constraints on BEOL manufacturability imposed by linewidth variability, random defects, signal integrity, and electromigration are considered for 250 and 180 nm technology. Our 250 nm projections are based on available information about Intel´s 250 nm Katmai microprocessor. This design has been extended to 180 nm by doubling logic and memory. We find that signal integrity is the greatest constraint and this could be alleviated by going to copper technology

Keywords

CMOS integrated circuits; integrated circuit interconnections; microprocessor chips; 180 nm; 250 nm; BEOL manufacturing; Cu; Intel Katmai microprocessor; copper technology; deep-submicron CMOS device; electromigration; interconnect; linewidth variability; random defects; signal integrity; CMOS logic circuits; CMOS technology; Clocks; Delay effects; Electromigration; Manufacturing; Microprocessors; Space technology; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5217-3

Type

conf

DOI

10.1109/ASMC.1999.798251

Filename

798251