• DocumentCode
    3232552
  • Title

    Analysis and reduction of defects induced by in-line wafer probing

  • Author

    Polavarapu, M. ; Peters, J. ; Wright, S.

  • Author_Institution
    Semicond. Technol. Center, Lockheed Martin Fed. Syst., Manassas, VA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    321
  • Lastpage
    322
  • Abstract
    Parametric and defect testing of drop-in or scribe line test structures after first level metal patterning is highly desirable since it offers rapid feedback for device or defect related issues in the front end of the line (FEOL). This assumes even more significance considering the dramatic increase in the levels of metallization made available by the chemical-mechanical polishing (CMP) technology and the corresponding increase in cycle time in the Back End Of the Line (BEOL). However, the potential for introduction of defects from such a seemingly innocuous operation as in-line test is frequently overlooked. This paper describes the significance of such defects, a method of monitoring the defect levels and the steps taken to reduce them
  • Keywords
    inspection; integrated circuit testing; integrated circuit yield; life testing; production testing; BEOL; CMOS reliability; SRAM qualification; bridging fails; defect testing; defects analysis; defects reduction; in-line wafer probing; life test; parametric testing; yield enhancement; Aluminum; Chemical technology; Feedback; Integrated circuit technology; Life testing; Qualifications; Semiconductor device reliability; Semiconductor device testing; Space technology; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI
  • Conference_Location
    Boston, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-5217-3
  • Type

    conf

  • DOI
    10.1109/ASMC.1999.798255
  • Filename
    798255