• DocumentCode
    3232627
  • Title

    Design Tools for Emerging Technologies

  • Author

    Johnson, S. ; Avniel, Y. ; White, J. ; Boyd, S.

  • Author_Institution
    Massachusetts Inst. of Technol., Cambridge, MA
  • fYear
    2006
  • fDate
    6-8 Sept. 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The rapidly expanding diversity of technology available at the nanoscale is disrupting the existing transistor-centric microelectronics design paradigm, resulting in nearly decade-long delays between prototype demonstration and technology deployment. The key to reducing these innovation-inhibiting delays is to develop algorithmic approaches that can start with first principles based descriptions of novel nanotechnology and rapidly and reliably synthesize manufacturable designs. Design tools are evolving this direction, with new extremely efficient yet customizable physical simulators, automatic parameterized low-order model extraction, and ever improving algorithms for robust optimization-new techniques that generate manufacturable designs by optimizing both system performance and robustness to manufacturing variations. In this paper we give a few examples of the coupling of such approaches, but mostly offer pointers to literature for researchers interested in contributed to this rapidly growing field of coupled simulation and robust optimization
  • Keywords
    design for manufacture; integrated circuit design; molecular electronics; nanoelectronics; transistors; automatic parameterized low-order model extraction; innovation-inhibiting delays reduction; nanotechnology; physical simulators; robust optimization techniques; transistor-centric microelectronics design paradigm; Algorithm design and analysis; Delay; Design optimization; Manufacturing automation; Microelectronics; Nanotechnology; Prototypes; Robustness; System performance; Virtual manufacturing; computer-aided design; nanotechnology; optimization; simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices, 2006 International Conference on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    1-4244-0404-5
  • Type

    conf

  • DOI
    10.1109/SISPAD.2006.282825
  • Filename
    4061568